5th Workshop on SoCs, Heterogeneous Architectures and Workloads (SHAW-5)

February 16th 2014, Orlando, Florida


Held in conjunction with HPCA-20



Workshop Final Program (Click here)


Organizing Chairs:

Ramesh Illikkal (Intel Labs)                      ramesh.g.illikkal@intel.com

Ravi Iyer (Intel Labs)                                ravishankar.iyer@intel.com

Raj Yavatkar (Intel)                                  raj.yavatkar@intel.com

Renato Figueiredo (University of Florida) renato@acis.ufl.edu



Computing platforms are getting smaller (e.g. handheld devices, wearables), richer (e.g. image and language understanding) and broader (i.e. reaching the masses via Internet of Things). This trend is made possible by System-on-Chip (SoC) and Heterogeneous Architectures that combine wider power/performance scaling, combinations of high performance and ultra-low power general-purpose cores along with a wide spectrum of domain-specific accelerators or Intellectual Property (IP) blocks. With the recent introduction of general-purpose compute cores such as Intel® Core™ i7 and Atom™ processors and the recently announced Quark processor, these heterogeneous platforms have the potential to run a much broader range of applications than ever before. The goal of this workshop is to bring together academic researchers and industry practitioners to discuss future SoC and Heterogeneous architectures, Accelerators and Workloads. The research challenges in SoC/Heterogeneous platforms are multi-fold: (a) providing rich functionality and wider power/performance range (b) attempting to cover a broad range of applications that can be migrated from mainstream platforms to SoCs and Heterogeneous devices, (c) enabling a modular architecture and design environment that improves time-to-market and (d) providing a rich software programming environment that eases the challenge of developing applications on a heterogeneous architecture consisting of general-purpose cores as well as specialized accelerators.

Below is the proposed list of topics for the workshop.  Topics include, but are not restricted to, the following:

          Novel SoC/Hetero Architectures

-    Architectures for wearable and IOT devices

-    Heterogeneity in Cores, Frequency, Cache, Memory

-    Different levels of Heterogeneity

-    Power, Performance, Energy optimizations

-    SoCs, CPU/GPU, CPU/GPGPU architectures

-    End-to-end heterogeneity (device-cloud offloads)

-    Ultra-Low Power Core Micro-architectures

-    Fabrics / Network-on-chip, Cache/Memory Hierarchies

-    HW Support for Heterogeneity, Programmability, Modularity

-    Simulation / Emulation Methodologies

          Emerging Workloads and Embedded Devices

-   New Workloads (Wearable/IOT usages)

-   Speech/Image recognition and understanding, Cognitive computing

-   Personal Assistants, Predictive/Prescriptive Analytics

-   Machine Learning Algorithms & Applications

-   Graph processing, Deep Neural Networks

-   Emerging embedded applications, devices and novel uses cases

-   Workload Analysis for power/performance/energy optimization and acceleration

-   Workload Partitioning between Heterogeneous Cores and Accelerators

-   Performance Monitoring and Simulation

-   Case Studies of SoC/Heterogeneous applications

          Novel Accelerator Designs

-   Specialized Accelerator Architectures and Designs

-   Machine Learning, Neural Network and Graph Processing accelerators

-   Domain-Specific Programmable/Configurable Accelerators

-   Accelerator Interfaces for Programmability

-   Development Environments for Accelerator Design


Submission Guidelines: Interested authors are encouraged to submit extended abstracts (1 - 2 pages) or short papers (6 pages) by email to the organizing chairs. The deadline for submission is December 23rd. Final (short) papers will be due on Jan 31st, 2014 and will be printed in a workshop proceedings made available to the workshop attendees.

Important Dates:

Abstract / Paper Submission

December 23, 2013

Author Notification

January 10, 2014

Final Paper Submission

January 31, 2014


February 16, 2014


Call for papers: Click here

Workshop Final Program: Click here


SHAW 2014 - Final Program

9:00 AM

9:05 AM

Workshop Introduction & Opening remarks



9:05 AM

9:40 AM

A Future Evolution in the Dimensionality of Systems Architecture (Invited talk)

Dr. Phil Emma, Chief Scientist

IBM Research

9:40 AM

10:05 AM

Hardware Acceleration of Sparse Matrix-Vector Multiply

Bong Jin Ko†‡ Jin Min Kim‡ Kyungsang Cho†‡ Jae W. Lee‡

†Samsung Electronics ‡Sungkyunkwan University Yongin, Korea Suwon, Korea

10:05 AM

10:35 AM




10:35 AM

11:00 AM

A Low-power Neural Network using Approximate Computing

Somnath Paul, Julio C Zamora Esquivel , Caleb Lo, Charles Augustine, Li Zhao

Intel Corporation

11:00 AM

11:25 AM

A New Composite CPU/Memory Model for Predicting Efficiency of Multi-core Processing

Khondker S. Hasan,
John K. Antonio, and
Sridhar Radhakrishnan

School of Computer Science University of Oklahoma Norman, OK, USA

11:25 AM

11:50 AM

Performance Predication Model for Heterogeneous Multicore Architectures : A Machine Learning Approach

Bin Li*, Li Zhao*, 
Andrew Herdrich* and
Sada Srinivasan § 

 *Intel Labs, Hillsboro, OR, U.S.A.
 §AMD, Austin, TX, U.S.A. 

11:50 AM

1:30 PM

 Lunch break

1:30 PM

2:05 PM

Synergistic Power-Management and QoS in Future Chip-Multiprocessors (Invited talk)

Dr. Paul V. Gratz

Department of
Electrical and Computer Engineering at Texas A&M University

2:05 PM

2:30 PM

A Transparent Multiple-ISA MPSoC Architecture  

Anderson Sartor, Fernanda M. Capella, Marcelo Brandalero, Luigi Carro, Antonio C. S. Beck

Instituto de Informática - Universidade Federal do Rio Grande do Sul - Porto Alegre, Brazil

2:30 PM

2:55 PM

Trustworthy SoC Architecture with On-Demand Security Policies and HW-SW Cooperation

Yier Jin1 and
Daniela Oliveira2

1Department of Electrical Engineering and Computer Science, University of Central Florida 2Department of Computer Science, Bowdoin College

2:55 PM

3:30 PM


3:30 PM

4:05 PM

OpenCL High-Level Synthesis for Mainstream FPGA Acceleration

Dr. Greg Stitt

University of Florida

4:05 PM

4:30 PM

Using monitors to predict co-running safety-critical hard real-time benchmark behavior

Jingyi Bin, Sylvain Girbal, Daniel Gracia P´erez and Alain Merigot

Fundamental Electronic Institute, France †Thales Research & Technology, France

4:30 PM

4:55 PM

Profiling EEMBC MultiBench Programs using Full-system Simulations

Chao Chen1, Ajay Joshi1, and Erno Salminen2

1Electrical and Computer Engineering Department,
Boston University, Boston, MA
2Department of Pervasive Computing, Tampere University of Technology, Finland